communication with 3.3V devices with cyclone 3

Hello,

following the Cyclone III manual and particularily table 7-8 acceptable input and output levels, 3.3V logic should be driven by a VCCIO of 3.3V. Driving inputs in a 2.5V bank from 3.3V is possible, but Altera requires proper termination to prevent overshoot and possible IO buffer damage at the input. The topic isn't new, but hasn't been presented that detailed before Cyclone III, see e. g. AN447.

The recommendation of 3.3V VCCIO for driving 3.3V logic allows to meet the minimum VOH level of the voltage standard (0.7 x 3.3 = 2.1 V) also with a loaded output and supply voltage tolerances as required by specification. You may however decide, that no additional load must be taken into account and use 2.5V VCCIO. As the typical VTH is 1.65 V, you get sufficicient noise margin in normal operation. Transition times may be however sligthly unsymmetric. Inputs with LVT characteristics (as Altera CPLD and FPGA itself) can be driven without restrictions anyway.

Regards,

Frank