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Honored Contributorcombine the quartus projects
Hi, are new for this forum, I need a help:
I have a DE1 card, I created a project to implement the fft through Mega Wizard Plug-In, I did the same thing to do a fir filter. I want to know how can I link the two projects, so that the output of the fft become the inputs of the fir filter. Thank you10 Replies
Altera_Forum--- Quote Start --- Hi, are new for this forum, I need a help: I have a DE1 card, I created a project to implement the fft through Mega Wizard Plug-In, I did the same thing to do a fir filter. I want to know how can I link the two projects, so that the output of the fft become the inputs of the fir filter. Thank you --- Quote End --- Hi, why did you create two different projects ? Only for testing ? What kind of design description are you using ? Verilog, VHDL ??? Kind regards GPK- Altera_Forum
Hi pletz,
I created two projects separately to make them test. The language that I use is the vhdl. Thank you for your answer - Altera_Forum--- Quote Start --- Hi pletz, I created two projects separately to make them test. The language that I use is the vhdl. Thank you for your answer --- Quote End --- Hi, write a toplevel in VHDL with the the two blocks as instances. Kind regards GPK
- Altera_Forum--- Quote Start --- Hi, write a toplevel in VHDL with the the two blocks as instances. Kind regards GPK --- Quote End --- Hi How do I call two blocks as instances? In vhdl not had never done something similar, I thought there was an automatic procedure
- Altera_Forum--- Quote Start --- Hi How do I call two blocks as instances? In vhdl not had never done something similar, I thought there was an automatic procedure --- Quote End --- Hi, no you have to write a toplevel on your own. Unfortunately I'm using Verilog and I have not so much expierence with VHDL. Kind regards GPK
- Altera_Forum
Thank you for your time
- Altera_Forum
hmm... here my situation is that 2 engineers were designing a project. i was makiing internal part (processing etc,) and my co worker was doing interfacing with surrounding chips. now we have our own projects own pin assignments (of cource they are in seperate banks.) if ill make my procet's symbol and he'l make he's; yes we may put these two symbols side by syde and connect them but which one will be the top level project? and how about 200 pins on each side? these pins now remain inside
in these projects... if we will get these pins on top level this creates hundreds of other problems. any solutions... ? im sure there is some way, people all around the world make huge projects each of them is devided across tens of engineers, there must be some way they link their work. - Altera_Forum
I see two solutions: you can either merge the two top level files manually, picking up the contents from both projects, or make a new top level file that contains all the pins, instantiate the two top level files you have now, and connect the pins to the instantiated components.
- Altera_Forum
yes i have came to that second way too. one problem was that when i change my project, it changes the project's symbol; and all the pin sequence aswell(inside the symbol). which means i will have to readjust all the pin connections. so i used "generate pins for symbol ports" button and it resolved the problem. assigned pin assignments from both projects files, worked fine. looks like this is the most comfortable way. short and smart. one big problem that remains, is that i have to go into add/remove files in quartus, and add all the coworkers project files in there manually, imagine 15modules of bsd,bsf,v,tdf files. that takes time.. but fortunetly you do it once and thats all.
one more thing, there is a big possibility that you and your co workers named their pins exactly same way you did. like clock27Mhz or something. that will lead to bigger problem when merging assignments from all projects. simply because one of the same names will overwrite another on top of it. and the pin location of one of the ports, will be erased in pin planner. im guessing quartus will generate an error that names are same for more than one ports, but i found more better solution. there is a free software called Kdiff3 .it is a text comparator soft. in it,there are 2 windows side by side. you open your assignments file in one window, co workers assignments file in a neighboring window; and Kdiff3 automatically compares two texts, it will light up unlike fields and like fields. that helps to track the similar names and change them. just sharing experience; hope it'l save someone. - Altera_Forum
When working with a team on the same FPGA I find it easier to do the top level file first. Create a project with all the pins, and that goes down to one hierarchy level with one box per sub project. Connect the boxes to the pins, define the interfaces between the boxes, and then distribute that "empty" project to everyone and have each one work on his part. Then it is a lot easier to merge everything back together, even during intermediary phases of the project to check that the subprojects work well together.
