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Majo's avatar
Majo
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2 years ago

Combine PCIE and SGMIIs in QSYS structure Cyclone V

Hi, I use PCIE HIP in Cyclone V wrapped into QSYS structure. Is it possible to add multiple (3 ports) of TRI Ethernet (SGMII) IPs to this existed PCIE QSYS structure? I have succeeded to add only 1 ...
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Majo's avatar
Majo
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2 years ago

Hi Wincent,

Thank you for your assistance. I could compile one PCIE and couple SGMII interfaces in one QSYS project when I set the common reference clock 125 MHz for all transceivers. I believe that combination helps to use a common TX PLL for all transceivers.

BR, Majo