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Honored Contributor
Honored ContributorCoding style to minimize combinational path delay?
I'm tuning my logic to meet timing. I have a long continuous assignment statement that outputs a signal based on the current state in my FSM. The below implementation results in a long mux chain. Is ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I wonder if grouping the select lines helps since it reduces the number of inputs... --- Quote End --- The expression for each bit of tx_tlp_dword_offset will undergo logic minimization during synthesis, thus I won't expect an effect of reordering or grouping on logic element usage. Different ways of state encoding matter, in contrast.
