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Altera_Forum
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14 years ago

Coding style to minimize combinational path delay?

I'm tuning my logic to meet timing. I have a long continuous assignment statement that outputs a signal based on the current state in my FSM. The below implementation results in a long mux chain. Is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I wonder if grouping the select lines helps since it reduces the number of inputs...

(I omitted the specific conditions that chose 7'h0 as an input since that will be taken care of by the default condition) 

assign tx_tlp_dword_offset = 
		(curstate == HANDLE_BAR1_READ_1_STATE) ? 7'h4 : 
		(curstate == HANDLE_BAR1_READ_3_STATE || 
                 curstate == H2D_DMA_INIT_MEMRD_DW1_STATE || 
                 curstate == D2H_DMA_INIT_MEMWR_DW1_STATE) ? 7'h1 : 
		(curstate == HANDLE_BAR1_READ_4_STATE || 
                 curstate == H2D_DMA_INIT_MEMRD_DW2_STATE ||
                 curstate == D2H_DMA_INIT_MEMWR_DW2_STATE) ? 7'h2 : 
		(curstate == HANDLE_BAR1_READ_5_STATE || 
		(curstate == HANDLE_BAR1_READ_6_STATE) ? 7'h5 :
		(curstate == H2D_DMA_INIT_MEMRD_DW3_STATE ||
		(curstate == H2D_DMA_SEND_MEMRD_TLP_STATE ||
		(curstate == H2D_DMA_SEND_MEMRD_TLP2_STATE) ? 7'h3 : 
		(curstate == D2H_DMA_INIT_MEMWR_PL_STATE) ? reg_tx_tlp_dword_offset : 
		(curstate == D2H_DMA_SEND_MEMWR_TLP_STATE) ? reg_tx_tlp_dword_offset : 
		(curstate == D2H_DMA_SEND_MEMWR_TLP2_STATE) ? reg_tx_tlp_dword_offset : 
		7'h0;