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Altera_Forum
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13 years ago

Coding style to minimize combinational path delay?

I'm tuning my logic to meet timing. I have a long continuous assignment statement that outputs a signal based on the current state in my FSM. The below implementation results in a long mux chain. Is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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In no vhdl expert, but maybe use single bit values for each of the 'curstate' values so that each line becomes: 

(curstate & XXX ? 7'hx : 0) |
which is simple logic.

Dunno if that ?: gets optimised away (easy to do).

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QII normally optimizes the state machine encoding to use 1-hot (or rather one signal per state) but i'm not too fond of this state encoding because it is harder to interpret in my signaltap trace (easier to see a number when looking for a particular state). I may have to go that route to optimize things though.