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Altera_Forum
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14 years ago

Coding style to minimize combinational path delay?

I'm tuning my logic to meet timing. I have a long continuous assignment statement that outputs a signal based on the current state in my FSM. The below implementation results in a long mux chain. Is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In no vhdl expert, but maybe use single bit values for each of the 'curstate' values so that each line becomes: 

(curstate & XXX ? 7'hx : 0) |
which is simple logic.

Dunno if that ?: gets optimised away (easy to do).