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Altera_Forum
Honored Contributor
Honored ContributorCode Optimization for FPGA
I was told the multiplier "*" in the code blow will dramatically slow down the operating speed(Fmax) of FPGA. But i don't konw why. Could somebody give me some hints on it? Any idea to optimize it? ...
Altera_ForumHonored Contributor
Honored ContributorMy understanding is that the compiler inserts a multiplier for each inference occurrence in a construct.
you can keep the construct but remove mult inference, use one mult and use the constrcut as switch for multiplier input
