code not working not sure why. code is posted along with megawizard code.

I am trying to use the megawizard function for the mif.

code:

LIBRARY IEEE;

--USE ieee.std_logic_vector.1164.all;

entity test is

GENERIC(depth: INTEGER := 256; mem_width: INTEGER := 8);

port(

--wr_ena: IN STD_LOGIC;

clk: IN STD_LOGIC;

addr: IN INTEGER RANGE 0 to depth-1;

data_in: IN STD_ULOGIC_VECTOR(mem_width-1 downto 0);

data_out: OUT STD_ULOGIC_VECTOR(mem_width-1 downto 0)

);

end entity test;

architecture async_ram of test is

component ch_13_ram_2p is

PORT (

address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

clock : IN STD_LOGIC := '1';

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

wren_a : IN STD_LOGIC := '0';

wren_b : IN STD_LOGIC := '0';

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END COMPONENT;

attribute ch_13_ram_2p: string;

attribute ch_13_ram_2p of myRAM: SIGNAL IS "ch13_ram_2p.mif";

BEGIN

myRAM: ch_13_ram_2p PORT MAP(

clock => clk,

address_a => addr,

address_b => addr,

data_a => data_in,

data_b => data_in,

wren_a => wr_ena,

wren_b => wr_ena,

q_a => data_out_a,

q_b => data_out_b);

END async_ram;

***********************************************************************

here is the file created from the megawizard plug-in

********************************************************************************

-- megafunction wizard: %RAM: 2-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram

-- ============================================================

-- File Name: ch13_ram_2p.vhd

-- Megafunction Name(s):

-- altsyncram

--

-- Simulation Library Files(s):

-- altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition

-- ************************************************************

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY ch13_ram_2p IS

PORT

(

address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

clock : IN STD_LOGIC := '1';

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

wren_a : IN STD_LOGIC := '0';

wren_b : IN STD_LOGIC := '0';

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END ch13_ram_2p;

ARCHITECTURE SYN OF ch13_ram_2p IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);

COMPONENT altsyncram

GENERIC (

address_reg_b : STRING;

clock_enable_input_a : STRING;

clock_enable_input_b : STRING;

clock_enable_output_a : STRING;

clock_enable_output_b : STRING;

indata_reg_b : STRING;

intended_device_family : STRING;

lpm_type : STRING;

numwords_a : NATURAL;

numwords_b : NATURAL;

operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_aclr_b : STRING;

outdata_reg_a : STRING;

outdata_reg_b : STRING;

power_up_uninitialized : STRING;

read_during_write_mode_mixed_ports : STRING;

read_during_write_mode_port_a : STRING;

read_during_write_mode_port_b : STRING;

widthad_a : NATURAL;

widthad_b : NATURAL;

width_a : NATURAL;

width_b : NATURAL;

width_byteena_a : NATURAL;

width_byteena_b : NATURAL;

wrcontrol_wraddress_reg_b : STRING

);

PORT (

clock0 : IN STD_LOGIC ;

wren_a : IN STD_LOGIC ;

address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

wren_b : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END COMPONENT;

BEGIN

q_a <= sub_wire0(7 DOWNTO 0);

q_b <= sub_wire1(7 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

address_reg_b => "CLOCK0",

clock_enable_input_a => "BYPASS",

clock_enable_input_b => "BYPASS",

clock_enable_output_a => "BYPASS",

clock_enable_output_b => "BYPASS",

indata_reg_b => "CLOCK0",

intended_device_family => "Cyclone IV GX",

lpm_type => "altsyncram",

numwords_a => 32,

numwords_b => 32,

operation_mode => "BIDIR_DUAL_PORT",

outdata_aclr_a => "NONE",

outdata_aclr_b => "NONE",

outdata_reg_a => "CLOCK0",

outdata_reg_b => "CLOCK0",

power_up_uninitialized => "FALSE",

read_during_write_mode_mixed_ports => "DONT_CARE",

read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",

read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",

widthad_a => 5,

widthad_b => 5,

width_a => 8,

width_b => 8,

width_byteena_a => 1,

width_byteena_b => 1,

wrcontrol_wraddress_reg_b => "CLOCK0"

)

PORT MAP (

clock0 => clock,

wren_a => wren_a,

address_b => address_b,

data_b => data_b,

wren_b => wren_b,

address_a => address_a,

data_a => data_a,

q_a => sub_wire0,

q_b => sub_wire1

);

END SYN;

"0"

********************************************************************************************************************

code error

******************************************************************************************************************************

Error (10482): VHDL error at test.vhd(8): object "STD_LOGIC" is used but not declared

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning

Error: Peak virtual memory: 226 megabytes

Error: Processing ended: Sun Apr 17 12:55:48 2011

Error: Elapsed time: 00:00:01

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning

*****************************************************************************************************************************************

click on the firs error I go to the clk:IN STD_LOGIC; line, but I thought that I am setting it equal to clock towards the end???