Closing timing when extra levels of combinatorial logic is small inside of adder IP

I managed to close timing by writing a Verilog module performing 128 bit addition using 64-bit numbers. Each 128 bit number was split up into high and low 64-bit numbers. The high and low parts were added, and a carry bit added for overflow. This worked well and the timing recommendation went away. I had to create an instance of LPM_ADD_SUB where the operation is piplined over a number of clock cycles. The pipelining was added when an instance of the megafunction was created. The pipeline is added when using the GUI in Quartus to create an instance of the LPM_ADD_SUB.