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Honored Contributor
Honored ContributorClosing timing when extra levels of combinatorial logic is small inside of adder IP
I am trying to close timing using the Quartus Timing Analyzer recommendations. Unfortunately, it appears that there is always 1 additional level of combinatorial logic and this level always seems to...
Altera_ForumHonored Contributor
Honored ContributorThanks, kaz. Is this a timing recommendation that can be safety ignored, or is there a way to add additional pipeline registers inside of each IP module? I am assuming that I simply need to increase the pipeline latency when configuring the IP? Essentially, I still need to pipeline the calculation?
