Clock Skew doubt

Hello Kaz,

Here are some of my doubts;

-----------------Question 1--------------------

Lets say there are two registers [register_a and register_b]. Data goes from register_a to register_b. [in space register_a comes before register_b]. Let clock_a and clock_b be their respective clocks. Now the data is handled by two different clocks and therefore it is passing through different clock domains.

case 1: clock_a is same as clock_b

Here the Time Quest Analyzer automatically considers the setup to by one cycle [lets say this is 10ns] and then tries to meet the timing requirement by positioning the position of register_b so that the setup time and hold time are not violated.

case 2: if they are different clocks

Here the Time Quest Analyzer considers the setup time for the path to be the time units between the two consecutive rising edges[ lets say this time between rising edge of clock_a and clock_b is 2ns]. So, in this case the setup time is considered as 2ns and the maximum delay the data can have before reaching the input of the destination register is 2ns. lets assume this cannot be met during which I can use:

1. set_false_path

2. set_clocks_group

3. set_multicycle [if the rising edges between the two clocks coincide]

my questions:

a) In the above para I described the reason why I would cut the analysis of the unrelated clock domain. Is it the right reason to cut it ? :) When I decide to cut the unrelated clock domains, is it just to get less timing errors in the Time Quest Analyzer[TQA] and reduce the stain on the fitter?

b) By using option 1 and 2, I am telling the TQA not to analyze that path. Though it is clocked by two different clocks, some one has to make sure that the rising edge of clock_b doesn't appear before/after the latching window at register_b. Who takes care of this?

c) If this is the right way to use set_false_path then, even before compilation I will set false path between all the clock domains that have a different frequencies. Is it the right thing to do?.

-----------------Question 2--------------------

In the flash presentation "Switching to Time Quest Timing Analysis" [This is an Altera Legacy training] in slide 16:

a) Since Pll clock is delayed by 2ns shouldn't the 1st rising edge of "pll_clk" appear 2ns after 1st rising edge of "clock"? Its the other way around in the video!!

b) Why do they add +2 while calculating the slack?

Thanks,

AA