Clock Skew doubt

Hi AA,

Thanks for your words. I will now add part II so you may focus on further points:

Now, how does a timing tool control tSU/tH inside fpga (ignoring io registers i.e. first fpga register and last external register in chain):

Note: to visualise properly this discussion, you need to imagine two registers i.e. launch/latch registers as two successive nodes in space. At the same time you need to visualise two clock edges in time domain at each register that relate by finite delay.

1) tSU violation is avoided by restricting clock period to a minimum such that the data transition (tCO) of launch almost hits tSU of latch.

In other words:

Fmax = lowest of 1/[reg tCO + reg tSU + (data delay – clk delay)] across all launch/latch pairs.

This applies to [edge to next edge] setup relationship. i.e the setup relationship is between current launch edge and following latch edge. It may differ in various systems e.g. it could be with opposite edge relationship(rise-fall) or have multicycles.

2)tH violation is avoided in silicon fabrication stage by making sure clock is never delayed more than data (global lines being fast).

Except for very fast clocks, fmax has nothing to do with tH because fmax is based on data transition never hitting tSU window so how can it pass across clk edge and hit tH window, however, the tool will check tH with respect to current (not next) edge at latch register and normally tCO ensuers kicking data transition well away from tH window. Put in other words, the tH relationship is bwteen current launch edge with current latch edge.

Above discussion applies to classic tSU/tH requirement. With high speed requirements, the pulse/period duration (toggle rate) may obviously have their own restrictions. Moreover, tH violation may occur now despite silicon avoidance, i.e. if clock is very fast then data transition (decided by tCO) could be too close to current edge at latch register. When fmax is restricted due to these extras then it is termed simply “restricted fmax”.

Apart from the chain structure of launch/latch pairs, there are cases of feedback e.g. an accumulator where launch/latch is to the same one register. Here, the same rules apply as if they are a pair.

To improve fmax, one needs to add more registers(pipe) to breakup the cloud of logic in between a pair or in a feedback path. Alternatively, one can add more copies of same register if you want to avoid the pain of functionality balancing caused by extra pipe. In equation terms this helps reduce data delay factor.

To avoid tH violation, do not gate the clock. If it is localised then you may try delay the data involved.

For specific sections you may also consider clock phase rotation (using PLL) but this is more commonly done at io.