Clock Skew doubt

Hi,

Thanks. I want to master timing Analysis. Here's what I know:

1. At a latch register you need the data to be present at the register's input certain time units before the latch edge [Setup time of the register- T(setup)] and the data has to be stable at the input certain time units after the latch edge [Hold time of the register- T(hold)]. When these conditions are met the data will be latched and mata-stable condition at the output can be prevented.

2. Apart from T(setup) and T(hold) there is T(co) [the time units elapsed after the latch edge for the data to move from the registers input to the registers output].

3. In some documents any thing specific to Register is prefixed with the word "Micro". In my case Micro T(hold), Micro T(setup), Micro T(co).

4. Since registers are placed apart the time taken by the clock to arrive at the clock input at the farther register [say register b] will be greater than the time taken by the clock to arrive at register [say register a] present before the register b. This is called as clock skew.

5. Above four points are used to calculate "Internal Fmax of the system".

6. To calculate the external Fmax of the system I need to consider the "T(port -> input pin of the register)" and "T (output pin -> port)"

What is confusing me?

1. I dont understand the + and - associated with the timing parameters in the equations. Some times I feel they should have been + instead of -.

2. I dont understand how the setup and hold relation between the clocks is found.

3. Difficulty in understand what clock exception I have to use "set_false_path" etc. in my timing constraints.

Thanks!!

AA