Clock Skew doubt

You need to think of clock&data as two partners going hand in hand from launch register towards latch register. Ideally they should go at same speed through same natural delay. In practice one may lag behind.

FPGA vendors stress in their routing technology to make clock never late and additionally advice users not to gate it. So data is slightly delayed more than clock.

We are talking about delay values too small relative to clock period so data reading is not a problem but we are looking at register timing window scenarios.