Clock Skew doubt

That is for minimum clock period (fmax then = 1/that).

You can imagine this formula if you draw two clock edges and imagine two registers receiving them:

-----|------|------

.........1..2.........

1 is micro tco, 2 is micro tsu.

The tco is due to launch register. clock & data then go for latch register which has tsu(not to be touched by transition).

if data/clock arrive with zero difference then:

minimum period would be 1 + 2 only

if data is late (normally that is the case inside fpga) then add difference since data will not quickly hit tsu window.

if clock is late(not favoured) then subtract difference. Though this may seem to increase fmax but causes hold violations.