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Altera_Forum's avatar
Altera_Forum
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13 years ago

Clock signal source should not drive registers triggered by different clock edges

I'm getting the following warning:

Warning (308022): (Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.

Its caused by a state machine clocked by the pos edge of clk and then another piece of code that needs to use the state and change a signal at the falling edge of the clock.

Should I be very concerned about this warning? From what I read, it means that it may be harder for it to meet timing, but it can work. Is there another way to accomplish changing a signal on the opposite edge of the clock (compared to when the state changes)?

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I'm really new to timing constraints so I may not know what I'm doing there yet. I have attached the sdc file.

    --- Quote End ---

    You must also be fairly new to FPGA design, as your SDC indicates you are creating a lot of generated clocks. Your design sounds simple enough that one clock shoud be sufficient. Anything on a timescale shorter than that clock, eg., your serial port baud-rate generator, should be generating an enable control (pulse) for logic clocked by your main clock, not used as another clock.

    Cheers,

    Dave