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Altera_Forum's avatar
Altera_Forum
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15 years ago

clock setup problems!

hi, how can I solve problems of clock setup?

I set in Quartus this options:

1.Assignments -> settings -> Fitter Settings->Optimize hold Timing ->All Paths

2.Assignments -> settings -> Classic Timing anallyzer->Clock settings -> (

Clock_global fmax 50 Mhz

Clock_derived fmax 2.5 Mhz ---based on Clock_global

Clock_pll fmaz 150 Mhz ---based on Clock_global

)

I have problems of clock setup, one of this is:

Slack

-0.509 ns

fmax

139.37 MHz ( period = 7.175 ns )

From

interface_PWM:inst8|pwm:spi|lpm_dff0:b2v_inst3|lpm_ff:lpm_ff_component|dffs[0]

To

interface_PWM:inst8|pwm:spi|lpm_compare1:b2v_inst4|lpm_compare:lpm_compare_componen

From clk

t|cmpr_pji:auto_generated|ageb_dffe[0] altpll2:inst13|altpll:altpll_component|_clk0

To clk

altpll2:inst13|altpll:altpll_component|_clk0

Required setup relationship

6.666 ns

required longest P2p time

2.671 ns

Actual Longest p2p Time

3.180 ns

Help Me!! Thanks!

I must set other options in quartus?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Requires setup relationship is 6.666ns, so it's a setup path and optimize hold timing won't help it. The problem is the required longest p2p time is 2.671ns. That usually means you have clock skew on the domain. Break out the path and look at the clcok paths to the source and destination and see why they're different. You're data path is only 3.180ns, so it's fast and easily meets the requirement, it's the clock skew that's hurting you.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    So these problems are solved by modifying the code?

    There aren't other settings that can help me in the Quartus ?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Tools -> Advisors -> Timing Optimization Advisors is a good starting place for switches in Quartus to help with timing. I would recommend that for a data path problem, but if you have a clock skew problem, the cause of the clock skew should be addressed first. You may be aware of what it is, determined that it has to be, and evaluated that there is no way to reduce the skew, but if not, I would do that first.