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Altera_Forum
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18 years ago

Clock Pulse Generator

Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

It is me again. I tried implementing my design with no clock mux. I used memory clock enable to control how many clock pulses. Attached is the enable generation diagram and code.

However, I am still getting undesired behavior at frequency higher than 100MHz. I checked it using an output counter. Based on enable generation design, the number of clock pulse = count + 1.

For example, if I set count to 2 (0010), I will expect to read '3' (0011) from out_counter. However, sometimes I got '3', sometimes '7' (0111), sometimes '8' (1000).

I am running out of idea on this undesired behavior. Quartus report said I can achieve ~200MHz.

One more point. When I lowered down VCC, I will observe more undeterministic behavior. Any comments or ideas?

thanks in advance.