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Altera_Forum
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19 years ago

Clock Pulse Generator

Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

I changed my clock pulse generator to feed the out to serve as clock enable for MRAM. In my design, I have 2 clock source for MRAM, as attached.

The operation sequence desired is:

- sel = 0, do some configuration with using ext_clock

- change sel = 1

- set start = 1. output from clock pulse generator will feed to MRAM. The number of clock pulse depends on "count" value

Quartus give me a warning on gated/ripple clock at the output of clock mux. Anywhere to get rid of this? Btw, output of clock mux is promoted as global signal.

With the above implementation, I am still not able to get the desired number of clock pulses.

Anything wrong with my implementation? I am using Stratix I device.