Clock Pulse Generator

What's your symptom? One more or less clock then expected, like it's just not enabling/disabling the PLL output fast enough, or random stuff? I'm guessing the first.

What timing engine are you using? That 200MHz report(which leads me to believe you're doing the Classic) means a clock domain can run at 200MHz, i.e. the data path is less than 5ns(not counting clock skew, multicycles, etc.) You've got a path that enables a clock domain. How do you know if that's meeting timing? To be honest, I'm not even sure how to do this at first glance, since the output needs to disable the PLL before it has a chance to disable the next edge coming out(almost like the gating is synchronous). Also, I believe the PLL enable will disable all PLL outputs, which ends the clock to your counter module and makes it all a one-shot process.

If it's just a number of clocks internally, use the enable as an enable on all the registers. If it's a clock going off chip, I agree with Avatar and make a 2x clock that drives a toggle register(bringing you back down to 1x) and have the clock enable drive this register. Now everything is nicely synchronous and you should have an easier time doing proper timing analysis.