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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock problem

Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

sir your code is not working

Error (10482): VHDL error at clk200.vhd(2): object "std_logic" is used but not declared