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Altera_Forum
Honored Contributor
14 years agoClock problem
Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum
Honored Contributor
14 years agoUsing a clock signal generated from logic is commonly a bad practice. If you mean to use it, you should route it through a global clock line, but I believe this is not possible in MAX7000S since global clocks are required to come from dedicated pins (please check this point, I'm not sure).
The correct way of operation is usually clocking everything with the global clock (clk_in in your case) and then generating proper clock enable signals, one pulse wide, in order to control the lower frequency counters. You need to change your code into: if(count = 1250000) then clk_en <= 1; count <= 1; else clk_en <= 0; end if; Then your seconds counter would be something like this: if(clk_in'event and clk_in='1') then if (clk_en = 1) seconds <= seconds+1; end if; end if; Regards