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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock problem

Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The code is now ok, although I can't get the point of this assignment

--- Quote Start ---

-- Required in order to convert the sinewave to a square wave

clk_out <= not clk_in;

--- Quote End ---

If you mean that clk_in comes from the external oscillator as a sine wave, this assignment is actually useless. FPGA is a digital device, so clk_in would be automatically converted in a square wave when it pass through the fpga input port.