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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock problem

Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks you both or replying.

I was trying to eventually reduce the frequency from 25 MHZ into 1 HZ eventually so that I can output pulses that are 1 second long in duration. I thought I would start by dividing the frequency by 2 first. On the hardware I am using the 25 MHZ crystal output is converted into square waves using the NOT function. I am not entirely sure how your code divides the frequency by 2:

if(clk_in'event and clk_in='1') then

clk_out <= not clk_out;

Thanks to you both.