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Altera_Forum
Honored Contributor
Honored ContributorClock Pins in Cyclone V
Hello, If I want to connect HSMA_CLK_IN_P2/N2 (which refers to CLK7p/n on my 5CSXFC6D6F31C8NES) to a PLL, I have to place the PLL in one of the two quadrants on the right of the chip, am I righ...
Altera_ForumHonored Contributor
Honored ContributorI am trying to use two serdes with an external PLL and to connect them to the HSMC connector.
As I want to receive the tx-clock from the opposite side and also to send the tx-clock of my side, Quartus constrains the PLL's location to X0 Y74, otherwise it refuses to place the PLL. That is a problem as I want to configure the PLL to be able to switch between a clock on my board (not the tx-clock but an external clock) and the received clock (the tx-clock of the other side). I have still not managed to route one of the clock sources on the Cyclone V SoC Dev Board to this location.
