Clock Pins in Cyclone V

From the 'Clock Network Sources', page 4-7:

http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf (http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf)

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The CLK<#>n pins drive the PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs.

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If the dedicated clock pins can drive the PLLs via the global clock networks this suggests there are no restrictions as to which PLLs can be driven from any dedicated clock inputs. However, the document goes on to discuss jitter if the global or regional clock resources are used along with Altera's recommendations regarding the use of PLLs. Depending on your requirements selecting a PLL away from the edge with the dedicated clock input may or may not be appropriate.

As for using a single ended clock - no, this won't gain you anything. The physical layer clock signal (differential or single ended) is terminated in the IO cell, before being driven onto a clock network. Driving a single ended clock in won't help with internal routing or choice of PLL.