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Altera_Forum's avatar
Altera_Forum
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12 years ago

Clock pins for Stratix IV E FPGA

Hello, I am supposedly failing to figure out the correct clock pins for the Stratix IV FPGA. I want to drive a PLL with a 100MHz clock but from what I get from the reference manual, the clocks ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

What really drives the PLL placement is the clock pin you select as the source. You need to specify these manually. The Auto placer may not place it on a usable pin for the PLL. (Which is what I think happened in your error message.)

Pete