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Honored Contributor
Honored ContributorClock pins for Stratix IV E FPGA
Hello, I am supposedly failing to figure out the correct clock pins for the Stratix IV FPGA. I want to drive a PLL with a 100MHz clock but from what I get from the reference manual, the clocks ...
Altera_ForumHonored Contributor
Honored ContributorI have selected a random clock input for the PLL and I am getting this error:
"Error (176554): Can't place Top/Bottom or Left/Right PLL "PLL:inst6|altpll:altpll_component|PLL_altpll:auto_generated|pll1" -- I/O pin clock_in1 (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device"
