Clock pins for Stratix IV E FPGA

In the Altera FPGA's clocks driving the PLL must be connected to the dedicated clock inputs (or in the case of the Stratix IV) cascaded from an adjacent PLL.

Typically there 4 clock inputs dedicated to each PLL. The number of PLL's vary per device and the output connectivity can very depending on if it's a top/bottom PLL or left/right PLL.

So to figure this out:

1: First download the Stratix IV device handbook and study Chapter 5: Clock Networks and PLLs in Stratix IV Devices.

2: Note all the PLL's required in the system and capabilities required for those PLL's.

3: Determine if TOP/BOTTOM/LEFT/RIGHT PLL's fit the specific requirements.

4: Identify the specific clock pin(s) that drive the specific PLL's that fit your requirement for each PLL required in the design. Make sure you are not targeting the SAME physical PLL with all your clocks.

If you are stuck due to a board layout issue: IE the layout was done before the steps above were completed, You may be stuck,

or it may be doable, but with restricted jitter performance, depending on the specific issue with the layout.

Most often the problem is, someone hooked up all the clocks to clock inputs 0, 1, 2, 3, but they all go to only 1 PLL. But the design really needs 2 or more PLL's. So the synthesis tool can't place multiple PLL's into the same location dictated by the driving pin requirement.

Pete