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Altera_Forum
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10 years ago

clock mux, clock dividers and best clock constraints to use

hi, i have a slow speed system as follows - 20M refclk -> clk divider giving refclk/2, refclk/4 -> clk_mux (to select clock going into rest of the syste) -> clk_gate -> ciock going into rest ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I am asking about the point 4) mentioned by Zubin. How should the create_generated_clock statement look like when I can not mention master clock as the refclk, but to mention it the output of the clk_mux