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Honored Contributor
Honored Contributorclock mux, clock dividers and best clock constraints to use
hi, i have a slow speed system as follows - 20M refclk -> clk divider giving refclk/2, refclk/4 -> clk_mux (to select clock going into rest of the syste) -> clk_gate -> ciock going into rest ...
Altera_ForumHonored Contributor
Honored ContributorCould you please clarify use of the last point 4).
What kind of constraint is suitable for that last clock gate and how to write that.
