Altera_Forum
Honored Contributor
Honored Contributorclock loss detection
Hi all! Any ideas to build a fast and robust clock loss detector? A reference clock is available.
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Altera_ForumHonored Contributor
Honored ContributorA diagram is attached to clarify code.
--- Quote Start --- If i_CLK_TBC and i_CLK_REF are similar frequencies, then there is no way you can use a synchronizer. --- Quote End --- Why? Assume it is the same clock, then the second flipflop in the synchronizer stage is never set. In my opinion faster clocks are no problem, as long as the low time of the clock to be observed satisfies reset pulse width. And for slower clocks the generic of the counter must be increased.
