clock loss detection

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Here is some code for discussing.

Simulation works fine, but I am not sure if there are any pitfalls.

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Try synthesis too. A simulator will let you do anything that is valid in the language. A synthesis tool will generate additional warnings related to whether design is practical in hardware.

When you have multiple clocks, you need to be concerned about clock domain crossing logic. For example, lets say you have a way of reading the counters from the 50MHz domain, eg., you have a Qsys system in that domain. Here's some suggestions;

1) Generate an enable pulse in the 50MHz domain, eg., use a counter to generate a signal that goes high for say 100ms and then low. Or just manually assert a signal high and then low, and have a counter that counts how long you managed to assert the signal. This works nicely, as in software you can simply code;

- write to enable register (set the enable bit)

- delay 100ms

- write to enable register (clear the enable bit)

- read the counter to see how many 50MHz clocks the pulse was asserted

2) Synchronize the enable pulse across to the other clock domain.

3) Use the synchronized pulse to enable a counter in the second clock domain. That counter is clocked by your external clock source.

4) (Optional) Using the enable pulse, generate a handshake back into the other clock domain.

So long as you read the two counters when the enable pulse is deasserted, you do not need to worry about clock domain crossing logic for the counter with the external clock source.

As Kosh comments, sketch out the circuit components, and a timing diagram, then get it working in Modelsim, and try a synthesis test in Quartus.

Cheers,

Dave