clock loss detection

It looks like you have a reasonable idea by making use of counters for your detection. My concern with the current design is that it uses 2 clock inputs to the same process. Timing issues can (and most likely will) occur resulting in potentially incorrect behavior. While I know that it is perfectly acceptable to have more item in the sensitivity list (in the right situation), I would suggest trying to restrict yourself to a reset signal and a single clock (per process). Multiple processes (as you have done) are just fine.

Something else that may help you generate code would be to draw out the design you want to implement using D-flip flops (with 1 clock and 1 reset). Once you have done this, it shouldn't be too bad to write your VHDL to match your diagram.