clock loss detection

Here is some code for discussing.

entity CLOCK_CHECK1 is
generic
    (
    gi_MAX_CNT            : integer := 3
    );
port 
   (
   i_NCLR               : in std_logic ;                       -- global /clr
   i_CLK_REF            : in std_logic ;                                -- reference clock
    i_CLK_TBC            : in std_logic ;                                -- clk 2 b checked
    o_MISS_CLK            : out std_logic                                 --
   );
end CLOCK_CHECK1 ;
architecture A_CLOCK_CHECK1 of CLOCK_CHECK1 is
   signal s2_NRES_CLK_H    : std_logic_vector(1 downto 0) ;
   signal s2_NRES_CLK_L    : std_logic_vector(1 downto 0) ;
   signal si_CNT1            : integer range 0 to gi_MAX_CNT ;
begin 
   SYNC1: process(i_CLK_REF,i_NCLR,i_CLK_TBC)
   begin    
       if i_NCLR = '0' or i_CLK_TBC = '0' then
           s2_NRES_CLK_L    <= (others => '0') ;
       elsif i_CLK_REF'event and i_CLK_REF = '1' then
           s2_NRES_CLK_L    <= s2_NRES_CLK_L(0) & '1' ;
       end if;
       if i_NCLR = '0' or i_CLK_TBC = '1' then
           s2_NRES_CLK_H    <= (others => '0') ;
       elsif i_CLK_REF'event and i_CLK_REF = '1' then
           s2_NRES_CLK_H    <= s2_NRES_CLK_H(0) & '1' ;
       end if;
   end process SYNC1;
    CNT1: process(i_CLK_REF,i_NCLR,s2_NRES_CLK_H(1),s2_NRES_CLK_L(1))
   begin
       if i_NCLR = '0' or (s2_NRES_CLK_H(1) = '0' and s2_NRES_CLK_L(1) = '0') then
           si_CNT1    <= 0 ;
       elsif i_CLK_REF'event and i_CLK_REF = '1' then
           if si_CNT1 < gi_MAX_CNT then
               si_CNT1    <= si_CNT1 + 1 ;
           end if;
       end if;
   end process CNT1;
    REG1: process(i_CLK_REF,i_NCLR)
    begin
        if i_NCLR     = '0' then
           o_MISS_CLK    <= '0' ;
        elsif i_CLK_REF'event and i_CLK_REF = '1' then
            if si_CNT1 = gi_MAX_CNT then
                o_MISS_CLK    <= '1' ;
            else
                o_MISS_CLK    <= '0' ;
            end if;
        end if;
    end process REG1;
end A_CLOCK_CHECK1 ;