Honored ContributorPlease, can someone tell me how to generate a clock with a pll, i would have in outputs 8khz and 256khz in quartus and i like to simulate it in modelsim altera on using code vhdl.thanks
Honored Contributorit is very simple, you should add a PLL component in your SOPC system. befor generate your system you should chek the option<<creat simulator project>> that you allow to simulate your system.
Honored ContributorI could be wrong, but I don't think that the PLL can accept/output frequencies that low. Depending on what you are doing you might be able to use an edge detect on your 8kHz signal and then have a much faster running internal clock which is a multiple of 8kHz and 256KHz and use that and your clock ratio to generate a 256Khz, the jitter and skew on this would be terrible when compared to a PLL though, again all this depends on your needs, you can improve the jitter characteristics by using as high a frequency as possible inside the chip, you could also make sure you are using global clock networking to reduce skew problems (if you are worried about it). Or just buy a dedicated PLL :) .
Honored ContributorI all has been said in previous threads on the same topic. Yes you can cascade PLL clock dividers with Cyclone III and generate that low frequencies, although a counter would be the usual simple solution.
