--- Quote Start ---
Single bit or multibit can be synchronised by two stage registers. There is no difference between the two cases.
--- Quote End ---
I think, there's an important difference. Consider a two bit signal changing from "01" to "10". When synchronizing the signal with registers only, the receiver may read "00" or "11" once during the transient due to delay skew. You have to implement additional filter logic, e.g. wait until the signal has been read twice with identical result, or handshake. For incrementally changing counter values, e.g. a FIFO level, gray encoding is a solution.
Referring to the original question, it isn't clear if the two clocks can be possibly synchronized, or if the frequency ratio would prevent an synchronous transfer anyway.
Honored Contributor
