clock domain crossing between two PLLs (cyclone III)

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The latest after reconfiguring one PLL or setting diiferent frequencies, the clocks can't be synchronous any more. But individual binary signals can be easily synchronized by two DFFs, multi bit signals are more difficult, needing handshake synchronization or domain crossing FIFOs.

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Single bit or multibit can be synchronised by two stage registers. There is no difference between the two cases.

I think what you mean is that slow events can do with this synchroniser only while fast events like data buses changing every clock need also handshaking signals as in dc fifos