Clock Data Recovery in Stratix V Transceiver

Hello,

I'm working on a project where I'm using the Transceiver of Stratix V and it is operating at 2 Gbps. I'm trying to use the Clock Data Recovery (CDR) in Lock to Data (LTD) mode but the output is not as expected. It works fine when using Lock to reference (LTR) mode. In LTD, I'm asserting the rx_digitalreset signal after rx_is_lockedtodata stops toggling but it doesn't want to work properly.

So, what should I do? How can I make it function correctly?

Thanks