Clock connection problem of PRBS7 pattern

So, you need to drive your PRBS7 logic with a clock. I suggest you use (in the first instance) the 50MHz clock sourced from Y2. This source is driven into the U33 (the Stratix IV FPGA) on pin AR22. That should result in you seeing something appropriate on your oscilloscope.

With your project open in Quartus, select 'Assignments' -> 'Pin Planner'. Find the row with your clock input signal in. Under the 'Location' column type 'AR22'. This will connect the 50MHz clock source to the clock that drives your logic.

J16 & J17 are there to allow clocks to be driven OFF the board. As specified in the data you provided, these are driven from FPGA pins M20 & L20 respectively. Any signal you connect from your logic to these pins will appear on the connectors.

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Program says that data rate of channel 0 is "20*clk freq"

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What program? And what are you trying to achieve?

Regards,

Alex