Specifically referring to the EP4CE6 devices, which have a core voltage of 1.2V, what logic level should the CLK input pins be at? Do they reference the core 1.2V level or the VCCIO level of the ban...
--- Quote Start --- I believe it will depend on which I/O standard that you used for the CLK input pins. --- Quote End --- Thanks, that's what I was going to go with:)