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Altera_Forum's avatar
Altera_Forum
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17 years ago

clk & i/o assignment on FPGA Board

I am testing my chip design using Apex Nios 2 board. However, my design was not done based on it. Hence, I would like to know:

1. How to connect an external clock input (from crystal) to a FPGA Board

2. How to connect i/o signals with FPGA Board

I planned to utilize the 3.3V Expansion Prototype Connector. Is this the correct way? Is there any document that describe such "non-standard" usage of the i/o pins for Apex Nios 2?

This is the 1st time I using a FPGA Board, sorry if I can't describe the problem well.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    I am testing my chip design using Apex Nios 2 board. However, my design was not done based on it. Hence, I would like to know:

    1. How to connect an external clock input (from crystal) to a FPGA Board

    2. How to connect i/o signals with FPGA Board

    I planned to utilize the 3.3V Expansion Prototype Connector. Is this the correct way? Is there any document that describe such "non-standard" usage of the i/o pins for Apex Nios 2?

    This is the 1st time I using a FPGA Board, sorry if I can't describe the problem well.

    --- Quote End ---

    It appears that you want to communicate with your board with signals originating from outside the board. Can you write what kind of I/O interfaces your board has? For example, if it has interfaces like RS-422, then you can route your signals including the clock through this interface.