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DWoof's avatar
DWoof
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7 years ago

Clarification required regarding Stratix 10 PCIe MM interrupts?

When an interrupt is signalled on a PCIe IRQ line from my Qsys component, I can see the interrupt status bit being asserted at address 0x0040 in the PCIe CRA slave. I then acknowledge the interrupt ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

​Hie,

I am afraid the question/help requested here is not clear. Are you asking on whether the step to clear the bit at address 0x00040 in the CRA slave compulsory for MM IRQ interrupts?

Also please let me know if you are using "AVMM Hard IP +" or "AVMM Hard IP" or "AVST" as the PCIe IP in Quartus.

Regards,

Nathan