Clarification on HBM Capacity and AXI4 Interface for Agilex 7 M Series

Hello admaris,

Yes, the maximum HBM capacity is 32GB. However, those 32GB are split into two HBM stacks. There is only 16GB for each stack and we have to use two HBM IPs to fully utilize those 32GB.

https://www.intel.com/content/www/us/en/docs/programmable/773264/24-3/m-series-hbm2e-introduction.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/773264/24-3/axi4-interface-signals.html

A single NoC Initiator can talk to multiple NoC targets (HBM, DDR4, DDR5, LPDDR5). Those extra bits are used to select different targets.

Regarding clock frequency, please have a look at this document. It shows all clocking schemes of NoC.

https://www.intel.com/content/www/us/en/docs/programmable/788295/23-3/planning-noc-and-memory-solution-clocks.html

Thanks.