Forum Discussion

Himabindu's avatar
Himabindu
Icon for New Contributor rankNew Contributor
5 years ago

Cisco- Altera PHY issue

and we are using your PHY in one of our IM 8x10G ( IMA8Z) . SDK version : 4.0 CHIP id: TpDrv-tpo225_c1-0_13.tar.gz ISSUE: There is a customer issue on 8x10G IM that after system reload inte...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

The hyperlink in this forum that you pointed out is not accessible. In order to better understand this problem, the following info is helpful.


  1. What FPGA in this product? Arria 10 or Stratix 10?
  2. What Quartus version that you are using?
  3. Which IP was implemented in this product? Is this Low Latency 10G IP + 10G base KR?
  4. Out of how many boards having this problem?


If the rxFifoUnderflow indicates the FPGA PHY RX FIFO, which means the data might be corrupted or there is an error in transmission, it could be due to the noise/jitter or the RX clock recovery fail to lock. And yes, a reset could be helpful when the data was corrupted or an error happened.


Regards -SK


  • Himabindu's avatar
    Himabindu
    Icon for New Contributor rankNew Contributor
    5 years ago

    hi,

    Please find my answers to your questions:

      Q: What FPGA in this product? Arria 10 or Stratix 10?
      A==> Stratix-V
      Q: What Quartus version that you are using?
        A==> from our code we are using the SDK version 4.0
          tpDrv-tpo225_c1-0_13.tar.gz
          TpDrv-tpo425p_c1-0_11.tar.gz
      Q: Which IP was implemented in this product? Is this Low Latency 10G IP + 10G base KR?
        A===> its 10G base KR
      Q:Out of how many boards having this problem?
        A==> Currently seen in 1 as per customer report

    If the rxFifoUnderflow indicates the FPGA PHY RX FIFO, which means the data might be corrupted or there is an error in transmission, it could be due to the noise/jitter or the RX clock recovery fail to lock. And yes, a reset could be helpful when the data was corrupted or an error happened.

    ===> Do we need to debug when the issue occurs next time or without any further debug is it ok to implement the work around of RESET when such alarms are seen.

    In current scenario we have seen 'rxFifoUnderflow' but what about other scenarios and which all alarms do we need to apply this work around.

    yes, we have requested customer to make sure transmission device (here traffic generator) should be proper or try with another device than TG but as they recovered now not tried. Its been observed twice we want to make sure not to hit the issue due to our code and hence, requesting is there any solution or work around is MUST for it?