Forum Discussion
Altera_Forum
Honored Contributor
13 years agoSorry, still learning the lingo....
What I have is multiple locations in a state machine that could write to multiple elemnts of the decision array. I struggled with the inferred RAM a few weeks ago and although I understand the basics, I don't think I have a full appreciation for the paradigm. Besides my custom code, the decision array is accessed by a NIOS CPU. I believe that the Altera MM Slave architecture used to access it from the NIOS infers it as RAM (Thats what the syntehesizer says). When I tried to simply write to the decision array from more than 1 location in the state machine, the compiler and assembler runs out of memory (using web edition). Therefore, I created the circular buffer which appears to compile and synthesize. It also worked sporadically. You comment about trying to do 3 writes and additions prompted me define a SM that divides these up. Any explanations you could provide regarding inferred ram would be greatly appreciated. ME