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Altera_Forum
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17 years ago

CIII Configuration Schemes

Hello, I have a CIII and an EPCS4 device. I currently use the SFL configuration scheme, meaning that I download a new image via JTAG/ByteBlaster and allow the FPGA take care of the AS programm...
Altera_Forum's avatar
Altera_Forum
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17 years ago

It's certainly possible, but most likely undocumented as a whole. You'll find detail documentation of several protocol parts involved with this action. If you are designing a new FPGA board, I suggest to connect the AS memory directly to the processor intended to perform programming. There are also Altera software examples for embedded AS programming, I think.