Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello Stefania,
I'll try to help: There are two variants of JTAG programming discussed in here:- Volatile JTAG programming This kind of programming is commonly used for debugging purposes, when you want a fast programming of the device or use features like the Signal Tap Logic Analyzer. This file is commonly a so called *.sof file. After disconneting power, all configured data is lost.
- Nonvolatile JTAG programming of Active Serial Configuration Devices This kind of programming is used when you want to programm your active serial eeprom over JTAG. This is the case when you don't have the boardspace for an additional connector, or there are more than one device in your JTAG chain and want to configure them in one programming cycle. This is a typical production scenario. Then you will create a programming file with the boatloader for your fpga device and the configuration file for the eeprom. (Quartus II -> File -> Convert Programming File -> Generate *.jic File). After power on reset the Boatloader will disappear out of the FPGA and it is configured out of the active serial config prom