chess clock coding using quartus II

i have another problem like this

Error (10397): VHDL Event Expression error at timer.vhd(15): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S

Error (10658): VHDL Operator error at timer.vhd(15): failed to evaluate call to operator ""and""

Error: Can't elaborate top-level user hierarchy

one more thing i wanna ask you, the package should be written in the coding or separated?

Too all,

I may be completely wrong here, and Cempaka, please correct me if I am, but.....

This sure looks like Cempaka has been assigned a homework problem in a class somewhere and none of us are doing this person any good if we do all the work for him (her).

There are a lot of very basic items that can most likely be addressed if you look at the Altera WEB page, Training and take some of the free WEB training classes.

http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html

I would start at the top on the right, and work my way down.

Please let me know if I am wrong or missing the mark.

Avatar

actually its not a homework...its one of my project...

thank you avatar...